Image and video compression on ASIC/FPGA devices
Colibri, JPEG 2000 and VC-2 HQ are video codecs that deliver low latency and high quality. Next to the compression algorithms, we have developed competencies around the network transport of the compressed video stream. Thanks to our strong expertise in hardware design and video compression/transport, we deliver OEM solutions to transport audio/video over IP networks.
Our high quality/low latency codecs are used in broadcast, Pro AV, digital cinema, industrial and defense, among other applications.
Video Codec IP Cores
Our IP cores are available on FPGAs and ASICs. All the codecs are scalable and flexible to match the specific constraints of each application (latency, image format, performance).
They support various image resolution, frame rate and latency constraints. They are also suitable for very complex systems with very high image resolution (4K/8K or more) or ultra-low latency.
Colibri
Designed for AV over IP, Colibri is an optimized video codec to perfectly encode any graphical content while preserving a visually lossless quality for video/moving pictures for the main PRO-AV use cases: 4K60fps over 1GbE/2.5GbE.
Key features include:
- 100% Image quality on graphical content
- Very light codec – fits even the most cost-efficient FPGA’s
- Low DDR Usage
- Multiview
- Low Complexity for ASIC & FPGA
- Ideal for 4K60fps over 1GbE & 2.5GbE
- Zero Latency (24 lines of video)
- Ideal for KVM
- Easy Integration
JPEG 2000
This EMMY® award-winning IP core solution can encode or decode JPEG 2000 images and video with unrivaled quality, high-speed and compact footprint and compliance with the ISO/IEC 15444-1 specification. It has been successfully integrated by market leaders in digital cinema, broadcast, defense, storage and video surveillance applications.
Key Features Include:
- Highly scalable code (configurable to fit any requirement)
- Single chip solution for multi-channel
- Rate control with visual weights for optimized quality
- Ultra low latency
- Watermarking interface for Digital Cinema applications
- Region of Interest / Activity Zone coding
- Multiple quality / resolution layers
- Provided with our high efficiency memory controller (for FPGA)
- Easy integration thanks to the use of standard interfaces (AXI)
VC-2 HQ
The high quality profile and low delay syntax of VC-2 is used to achieve low compression ratio, typically up to 4 times visually lossless.
The algorithm is lightweight and works without external memory allowing cost-effective implementation.
The VC-2 High Quality codec has ultra-low latency due to its slice-based processing.
Key Features include:
- Low Complexity for ASIC & FPGA
- Extreme Low Latency: 0.0593 milliseconds!
- 8K Ready and Beyond
- No external DDR
- 100% Image Quality
- Lossless Compression
- SMPTE ST2042 & ST2110
- Patent Free
JPEG
The JPEG IP (Intellectual Property) cores are intended for high-speed encoding and decoding of images according to ISO/IEC 10918-1 baseline coding standard.
The IP cores can be used with both ASIC and FPGA families. As our JPEG cores are very compact it will also fit in smallest FPGA devices.
The encoding quality is fully configurable during run-time, including custom entropy and quantization tables.
Key features include:
- Compliance with baseline JPEG (ISO/IEC 10918-1)
- 8 bits per pixel only
- Unrestricted image resolutions up to 64K by 64K.
- Chroma subsampling (4:4:4, 4:2:2, 4:2:0), grayscale and bayer support.
- Full header building and parsing capability:
- user-definable comments
- application markers
- quantization tables
- Huffman tables
- Support for full-format and abbreviated-format, including restart markers and restart interval
MPEG-2
Our MPEG-2 decoder IP is optimized for applications such as broadcast, production, digital cinema, and video conferencing.
It delivers real-time decoding of high-resolution and multi-channel video streams such as 2K, 4K, SD, HD…
The flexible architecture provides the highest standards of portability, flexibility, performance and compactness.
Key features include:
- Portability: support for all leading-edge FPGAs
- Flexibility: easy to integrate interface
- Performance: faster than real-time to support more simultaneous channels, larger images or higher frame-rate
- Compactness: cost-effective, low resource count
- Interoperability: Compliant with MPEG-2 TS
Video Codec IP using RAW input (CFA)
The video IP cores using CFA (Bayer, Quad-Bayer) produces visually lossless video quality. The algorithm adds minimal latency to the system while it offers super-resolution.
The digital camera system is typically formed by a lens system, an image sensor and an image processing pipeline. When an image is captured, the scene is first illuminated by the camera flash or by ambient lighting. The light beams then travel through a lens system and reach an image sensor. The image sensor creates a digital representation of the captured light. Raw image data is read from the sensor and transferred into the image processing (demosaicing) pipeline. The demosaicing can take place within the FPGA/ASIC or done by software.
For real time applications where the compressed video is sent on the network, an implementation of a demosaicing algorithm on FPGA/ASIC is ideal thanks to the parallel processing nature of FPGA/ASIC’s.
Viper AV-over-IP Board
4K HDMI 60fps 4:4:4 HDMI to IP Transmitter/Receiver Board
A fully-integrated board that enables ultra-low latency AV over IP. The transmit and receive boards features up to 4K/UHD over 1GbE, 2.5GbE and 10GbE Ethernet cable with compression using the Colibri, VC-2 HQ, JPEG 2000 or another codec.
Ideal for:
Integrators and equipment manufacturers wanting to develop their own HDMI/USB-C AV over IP transmitter/receiver board with reduced investment and time-to-market.
Want to design your own PCB?
We can deliver the 4K60fps AVoIP transmitter/receiver chip, including all the same features as the Viper TX/RX board, for you to integrate in your own PCB design. Contact us below for more details.
Memory Controller
Ultra-High Pixel Rate Memory Controller Designed for Video Codec
Too often significant effort is invested into DDR memory access bandwidth optimization. We believe this is something which should just work out of the box and this ultra-high pixel rate memory controller does just that. Using innovative features to ensure unequalled bandwidth efficiency while maintaining ease of integration, flexible configuration and state of the art debug functionality results in faster time to market, higher performance and/or less DDR costs.
Video Codecs with improved performance
- JPEG 2000
- H.264/H.265
- VP8/VP9
- AV1
- …other
Features
- Ultra-efficient bandwidth usage
- Optional ping-pong support for even more efficiency
- ECC
- Ideal for FPGA integration:
- Synthesizable standalone BIST for on-target validation
- Efficiency monitoring
- Simulation tools